(VRV32Zicsr Control and Status Register (CSR) Instructions
p0
ccopy_reg
_reconstructor
p1
(cvp_pack
Ip
p2
c__builtin__
object
p3
Ntp4
Rp5
(dp6
Vprop_count
p7
I6
sVname
p8
g0
sVprop_list
p9
(dp10
sVip_num
p11
I13
sVwid_order
p12
I13
sVrfu_dict
p13
(dp14
sVrfu_list
p15
(lp16
(V000_CSRRW
p17
g1
(cvp_pack
Prop
p18
g3
Ntp19
Rp20
(dp21
Vitem_count
p22
I2
sg8
g17
sVtag
p23
VVP_IP007_P000
p24
sVitem_list
p25
(dp26
sg12
I0
sg15
(lp27
(V000
p28
g1
(cvp_pack
Item
p29
g3
Ntp30
Rp31
(dp32
g8
V000
p33
sg23
VVP_ISA_F007_S000_I000
p34
sVdescription
p35
Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1]
p36
sVpurpose
p37
VISA Chapter 9
p38
sVverif_goals
p39
VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used
p40
sVcoverage_loc
p41
V
p42
sVpfc
p43
I3
sVtest_type
p44
I3
sVcov_method
p45
I1
sVcores
p46
I56
sVcomments
p47
g42
sVstatus
p48
g42
sVsimu_target_list
p49
(lp50
sg15
(lp51
sVrfu_list_2
p52
(lp53
sg13
(dp54
Vlock_status
p55
I0
ssbtp56
a(V001
p57
g1
(g29
g3
Ntp58
Rp59
(dp60
g8
V001
p61
sg23
VVP_ISA_F007_S000_I001
p62
sg35
Vcsrrw rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1]
p63
sg37
VISA Chapter 9
p64
sg39
VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0)
p65
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp66
sg15
(lp67
sg52
(lp68
sg13
(dp69
g55
I0
ssbtp70
asVrfu_list_1
p71
(lp72
sg52
(lp73
sg13
(dp74
sbtp75
a(V001_CSRRS
p76
g1
(g18
g3
Ntp77
Rp78
(dp79
g22
I2
sg8
g76
sg23
VVP_IP007_P001
p80
sg25
(dp81
sg12
I1
sg15
(lp82
(V000
p83
g1
(g29
g3
Ntp84
Rp85
(dp86
g8
V000
p87
sg23
VVP_ISA_F007_S001_I000
p88
sg35
Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable.
p89
sg37
VISA Chapter 9
p90
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used
p91
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp92
sg15
(lp93
sg52
(lp94
sg13
(dp95
g55
I0
ssbtp96
a(V001
p97
g1
(g29
g3
Ntp98
Rp99
(dp100
g8
V001
p101
sg23
VVP_ISA_F007_S001_I001
p102
sg35
Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = [rs1] | csr\u000aNote that not all bits of csr will be writable.
p103
sg37
VISA Chapter 9
p104
sg39
VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0)
p105
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp106
sg15
(lp107
sg52
(lp108
sg13
(dp109
g55
I0
ssbtp110
asg71
(lp111
sg52
(lp112
sg13
(dp113
sbtp114
a(V002_CSRRC
p115
g1
(g18
g3
Ntp116
Rp117
(dp118
g22
I2
sg8
g115
sg23
VVP_IP007_P002
p119
sg25
(dp120
sg12
I2
sg15
(lp121
(V000
p122
g1
(g29
g3
Ntp123
Rp124
(dp125
g8
V000
p126
sg23
VVP_ISA_F007_S002_I000
p127
sg35
Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable.
p128
sg37
VISA Chapter 9
p129
sg39
VRegister operands:\u000a\u000aAll possible rs1 registers are used\u000aAll possible rd registers are used\u000aAll supported CSRs are used\u000aAll possible register combinations where rs1 == rd are used
p130
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp131
sg15
(lp132
sg52
(lp133
sg13
(dp134
g55
I0
ssbtp135
a(V001
p136
g1
(g29
g3
Ntp137
Rp138
(dp139
g8
V001
p140
sg23
VVP_ISA_F007_S002_I001
p141
sg35
Vcsrrs rd, rs1, csr\u000ard = Zext([csr]); csr = ~[rs1] | csr\u000aNote that not all bits of csr will be writable.
p142
sg37
VISA Chapter 9
p143
sg39
VInput operand:\u000a\u000aNon-zero and zero rs1 operands are used (if rs1 != x0)
p144
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp145
sg15
(lp146
sg52
(lp147
sg13
(dp148
g55
I0
ssbtp149
asg71
(lp150
sg52
(lp151
sg13
(dp152
sbtp153
a(V003_CSRRWI
p154
g1
(g18
g3
Ntp155
Rp156
(dp157
g22
I2
sg8
g154
sg23
VVP_IP007_P003
p158
sg25
(dp159
sg12
I3
sg15
(lp160
(V000
p161
g1
(g29
g3
Ntp162
Rp163
(dp164
g8
V000
p165
sg23
VVP_ISA_F007_S003_I000
p166
sg35
Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read.
p167
sg37
VISA Chapter 9
p168
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used
p169
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp170
sg15
(lp171
sg52
(lp172
sg13
(dp173
g55
I0
ssbtp174
a(V001
p175
g1
(g29
g3
Ntp176
Rp177
(dp178
g8
V001
p179
sg23
VVP_ISA_F007_S003_I001
p180
sg35
Vcsrrwi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0])\u000aIf rd == x0 then CSR is not read.
p181
sg37
VISA Chapter 9
p182
sg39
VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled
p183
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp184
sg15
(lp185
sg52
(lp186
sg13
(dp187
g55
I0
ssbtp188
asg71
(lp189
sg52
(lp190
sg13
(dp191
sbtp192
a(V004_CSRRSI
p193
g1
(g18
g3
Ntp194
Rp195
(dp196
g22
I2
sg8
g193
sg23
VVP_IP007_P004
p197
sg25
(dp198
sg12
I4
sg15
(lp199
(V000
p200
g1
(g29
g3
Ntp201
Rp202
(dp203
g8
V000
p204
sg23
VVP_ISA_F007_S004_I000
p205
sg35
Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable.
p206
sg37
VISA Chapter 9
p207
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used
p208
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp209
sg15
(lp210
sg52
(lp211
sg13
(dp212
g55
I0
ssbtp213
a(V001
p214
g1
(g29
g3
Ntp215
Rp216
(dp217
g8
V001
p218
sg23
VVP_ISA_F007_S004_I001
p219
sg35
Vcsrrsi rd, imm[4:0], csr\u000ard = Zext([csr]); csr = Zext(imm[4:0]) | csr\u000aNote that not all bits of csr will be writable.
p220
sg37
VISA Chapter 9
p221
sg39
VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled
p222
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp223
sg15
(lp224
sg52
(lp225
sg13
(dp226
g55
I0
ssbtp227
asg71
(lp228
sg52
(lp229
sg13
(dp230
sbtp231
a(V005_CSRRCI
p232
g1
(g18
g3
Ntp233
Rp234
(dp235
g22
I2
sg8
g232
sg23
VVP_IP007_P005
p236
sg25
(dp237
sg12
I5
sg15
(lp238
(V000
p239
g1
(g29
g3
Ntp240
Rp241
(dp242
g8
V000
p243
sg23
VVP_ISA_F007_S005_I000
p244
sg35
Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable.
p245
sg37
VISA Chapter 9
p246
sg39
VRegister operands:\u000a\u000aAll possible rd registers are used\u000aAll supported CSRs are used
p247
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp248
sg15
(lp249
sg52
(lp250
sg13
(dp251
g55
I0
ssbtp252
a(V001
p253
g1
(g29
g3
Ntp254
Rp255
(dp256
g8
V001
p257
sg23
VVP_ISA_F007_S005_I001
p258
sg35
Vcsrrs rd, imm[4:0], csr\u000ard = Zext([csr]); csr = ~(Zext(imm[4:0])) | csr\u000aNote that not all bits of csr will be writable.
p259
sg37
VISA Chapter 9
p260
sg39
VInput operand:\u000a\u000aNon-zero and zero imm[4:0] operands are used\u000aAll bits of imm[4:0] are toggled
p261
sg41
g42
sg43
I3
sg44
I3
sg45
I1
sg46
I56
sg47
g42
sg48
g42
sg49
(lp262
sg15
(lp263
sg52
(lp264
sg13
(dp265
g55
I0
ssbtp266
asg71
(lp267
sg52
(lp268
sg13
(dp269
sbtp270
asVrfu_list_0
p271
(lp272
sg71
(lp273
sVvptool_gitrev
p274
V$Id: af214b54d38e440023a14011aefff4dabfd5f5ad $
p275
sVio_fmt_gitrev
p276
V$Id: 052d0c6f3d12d7984d208b14555a56b2f0c2485d $
p277
sVconfig_gitrev
p278
V$Id: 0422e19126dae20ffc4d5a84e4ce3de0b6eb4eb5 $
p279
sVymlcfg_gitrev
p280
V$Id: 286c689bd48b7a58f9a37754267895cffef1270c $
p281
sbtp282
.